Vector: SIL Kit¶

Vendor information

Vendor	Web page	Product name	Version
Vector Informatik GmbH	https://github.com/vectorgrp/sil-kit/	The Vector SIL Kit	v4.0.19, tested up to v5.0.6

File format	Comment
*.asc
*.mf4	BUSACCESS - CAN(-FD) ports support MDF4 bus logging only. XCP ports support signal-based MDF4 recording.
*.pcapng	BUSACCESS - CAN(-FD) ports will use linktype=227. The resulting files cannot be processed by trace analysis.

Operating system	Support
Windows	✓
Linux	✓

Ports¶

Info

Ports marked with ✦ are part of the Add-on ecu.test calibration (subject to a separate license)

Specifics¶

This interface allows direct access to simulated Ethernet as well as CAN, CAN-FD, LIN and FlexRay buses. It supports the test steps read signal, read/write signal group (all bus systems) as well as monitor (CAN, CAN-FD, LIN and FlexRay) and supports signal recording (all bus systems), Raw diagnostics with KWP2000 over ISO-TP (CAN only), the Mini residual bus simulation (CAN, CAN-FD and FlexRay) and Additional functions of the close-to-hardware bus connections (all bus systems).

At the moment only the autonomous lifecycle mode is supported.

Prerequisites

The Vector SIL Kit must be available on the tool host. As it will not be installed, but extracted to an arbitrary folder, the path to SilKit.dll (Windows) or libSilKit.so (Linux) has to be entered in the TBC editor at tool level.
ecu.test will not attempt to start the SIL Kit registry, but expects it to be already running and available under the URI specified in the TBC.

Note on the use of ethernet ports

In order to exchange ethernet packets with other SIL Kit participants, the name of a suitable network as well as an arbitrary controller name must be entered in the TBC.

Info

Further informationen about the purposes of the various Ethernet port types and their differences can be found in the description of the tool adapter tracetronic: Ethernet. All those not ending in -RAW here except ARP correspond to a similarly named type with the suffix or infix -PCAP there.

Note on the use of FLX ports

FlexRay ports can only communicate if SIL Kit runs a detailed simulation using the NetworkSimulator. The NetworkSimulator is not part of the SIL Kit itself, but can be obtained from Vector Informatik GmbH.

Enable simulation time in ports¶

In order to use the simulation time in the ports, a MODELACCESS - DEFAULT port must be created and the tool option enable model time must be set to True. Without this selection, system time will be used rather than simulation time.

Simulation time control¶

Stepwise execution in simulation time¶

This mode is currently not supported.

Continuous execution in simulation time¶

In this mode, a SIL Kit participant created for that purpose streams the current simulation time to ecu.test. The simulation time affects the test case itself (e.g. Wait test steps or time options of evaluations). Furthermore, simulation time is applied within Ethernet communication protocols to fulfill cycle times, observe timeouts etc.

Properties 🛈¶

Name	Default value	Type	Description
SIL Kit Library Path		string	Path to SilKit.dll or libSilKit.so, as an absolute path or relative to the tool host’s base path
SIL Kit Registry URI	‘silkit://localhost:8500’	string	URI to the Sil Kit Registry Server
Activate model time	☐	bool	Use model time for all ports. When activated, a model port must be configured in the SIL Kit.
Timeout for tool call ❲in sec.❳	‘600’	string	Timeout after which a tool call is aborted.

Jobs 🛈¶

ClearArpCache¶

Clears all entries from the internal ARP/NDP cache